In a conventional computer system, a single processor, sometimes operating with either a built-in or add-on numeric processor carries out predefined instructions to control a machine, process data, or develop a solution to a problem. Although mainframe computers have been developed that achieve relatively high throughput, conventional low-cost desktop computers and minicomputers are typically limited to clock speeds of 33-50 MHz, depending on the type of central processing unit (CPU) employed. The throughput that can be achieved on such processors is too low for many real-time control applications that may include intelligent sensing or recognition of physical elements, complex data structures, extensive communications between elements in the system, and demands for shared data access.
Systems for applications such as real-time radar signal processing and machine control must readily handle fast symbolic computations and provide reliable, high throughput coupled with numeric and symbolic processing. One way to improve the throughput of lower cost computer systems is to use parallel processors that share the computational and control overhead. Unfortunately, prior art system architecture and computing hardware, whether using a single processor or multiple parallel processors, can not efficiently integrate such diverse functions as sensor processing, servo control, pattern recognition, navigation, trajectory planning, adaptive modeling, and reasoning, while still meeting performance throughput requirements.
To achieve these required levels of performance, a different type of processing configuration has been developed in the art. The new configuration is conceptually similar to the paradigm in which a group of people join in a brainstorming session to develop a solution to a problem. In such sessions, a solution is often developed by writing facts and any contributions by the participants on a blackboard so that the data and partial solutions to the problem developed by different members of the group are available to all of the members, thereby more efficiently producing a final solution to the problem. By analogy, the computational software configuration that carries out a comparable function is therefore called a blackboard processing system.
In the blackboard processing system, software components that directly process data to produce portions of a solution or components of the functional endpurpose of the system are referred to as knowledge sources. A multidimensional data structure comprising a centralized data base represents a dynamic problem solution state in the system and is called a blackboard. A blackboard processing system also typically includes a blackboard handler module, which is implemented either as a procedure called as a subroutine or as a process that contains a queue of requests for blackboard operations; the blackboard handler module passes read and write requests between the knowledge sources and the blackboard. This concept is described in detail in "Parallelism in Artificial Intelligence Problem Solving: A case Study of Hearsay II" by Richard D. Fennell and Victor R. Lesser, published in IEEE Transactions on Computers, Vol. C-26, No. 2, February 1977, pp. 98-111. In this paper, the blackboard system is applied to a speech understanding problem and is modeled in a multiprocessor simulation experiment run on a uniprocessor system. A multiprocessor hardware configuration suitable for a blackboard processor system is not disclosed in this reference, although application of the concept to a closely coupled network of asynchronous "simple" processors is discussed and possibly represents the goal of further development by the authors.
In U.S. Pat. No. 4,809,346 and a related U.S. Pat. No. 4,809,347, a computer vision architecture is disclosed. The system described in these two patents includes a host computer, a general purpose processor array, an intermediate communications processor, and content-addressable array parallel processors connected in a hierarchical configuration. The lowest order content-addressable array parallel processor operates on a pixel-per-processing element basis, while the higher level processors operate on successively larger segments of a pixel matrix and provide a relatively more symbolic processing function. In these references, a symbolic pixel array is referred to as "a blackboard" data structure that represents information at both the pixel level and the object level. However, the configuration disclosed in the two patents is not a blackboard processing system.
In U.S. Pat. No. 4,862,407, digital signal processing apparatus are disclosed that include a host processor in communication with a plurality of coprocessors via a corresponding plurality of dual port memory circuits. The reference states that the dual port memory elements serve the purpose of an intelligent blackboard or calculator to the host processor. However, the system described in this reference is not a blackboard processing system according to the normally accepted definition of the phrase, because the dual port memory circuits are not intelligent (i.e., do not carry out any processing or logic function), and the memory circuits do not monitor the state of the data input to a coprocessor or respond to the data output from the processor to activate further processing tasks. The use of the term "blackboard" in the three patents identified above is illustrative of the relatively wide variation in meaning that this terminology has in the prior art.
Consistent with the traditional model of a blackboard processing system, a plurality of independent processors should cooperate in solving a problem by posting data on a global blackboard data structure. In response to events occurring either externally or as a result of output from the processors, the global blackboard data structure should control the problem-solving activities of the processors, thereby dynamically adapting the tasks carried out by the processors to the current state of the solution. The blackboard processing system should be adaptable to solve new problems by simply reprogramming the system with appropriate parallel processing algorithms. Currently, no system of this power and flexibility exists in the prior art, except as defined by highly conceptual models that do not realistically have the capacity to achieve the required computational power that is an object of a true blackboard processing system. Accordingly, it should be apparent that a novel combined multiprocessor hardware and software system is needed to meet the demand for a faster, more powerful, and more highly integrated parallel processor system appropriate to achieve the expectations of the blackboard system paradigm.
The foregoing aspects and many of the attendant advantages of the present invention will become apparent by reference to the accompanying drawings and the Detailed Description of the Preferred Embodiments that follows.